V. Murali Praveen

[2] viXra:1405.0048 submitted on 2014-05-07 01:34:19, (255 unique-IP downloads)

Minimizing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme

Authors: A.saisudheer, V. Murali Praveen, S.jhansi Lakshmi
Category: Data Structures and Algorithms

[1] viXra:1405.0047 submitted on 2014-05-07 01:35:18, (128 unique-IP downloads)

SSBD: Single Side Buffered Deflection Router for On-Chip Networks

Authors: V.Sankaraiah, V.Murali Praveen
Category: Data Structures and Algorithms