Data Structures and Algorithms


SSBD: Single Side Buffered Deflection Router for On-Chip Networks

Authors: V.Sankaraiah, V.Murali Praveen

As technology scaling drives the no.of processors upward, current on-chip routers consume substantial portions of chip area, performance, cost & power budgets. Recent work proposes to apply well-known routing technique, which eliminate buffers & hence buffers power (static & dynamic) at the cost of some misrouting or deflection called bufferless deflection routing. While bufferless NoC design has shown promising area and power reductions and offers similar performance to conventional buffered for many workloads. Such design provides lower throughput, unnecessary networkhops and wasting power at high network loads. To address this issue we propose an innovative NoC router design called Single Side Buffered Defection (SSBD)router. Compared to previous bufferless deflection router SSBD contributes (i) a router microarchitecture with a double-width ejection path and enhanced arbitration with in-router prioritization. (ii)small side buffers to hold some traffic that would have otherwise been deflected.

Comments: 6 Pages.

Download: PDF

Submission history

[v1] 2014-05-07 01:35:18

Unique-IP document downloads: 147 times is a pre-print repository rather than a journal. Articles hosted may not yet have been verified by peer-review and should be treated as preliminary. In particular, anything that appears to include financial or legal advice or proposed medical treatments should be treated with due caution. will not be responsible for any consequences of actions that result from any form of use of any documents on this website.

Add your own feedback and questions here:
You are equally welcome to be positive or negative about any paper but please be polite. If you are being critical you must mention at least one specific error, otherwise your comment will be deleted as unhelpful.

comments powered by Disqus