Data Structures and Algorithms


Minimizing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme

Authors: A.saisudheer, V. Murali Praveen, S.jhansi Lakshmi

In this paper, a low-power pulse-triggered flip-flop (FF) designed and a simple two-transistor AND gate is designed to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulsegeneration circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 50-nm technology reveal that the proposed design features the best power-delay-product performance in several FF designs under comparison. Its maximum power saving against rival designs is up to 18.2% and the average leakage power consumption is also reduced by a factor of 1.52

Comments: 6 Pages.

Download: PDF

Submission history

[v1] 2014-05-07 01:34:19

Unique-IP document downloads: 255 times

Add your own feedback and questions here:
You are equally welcome to be positive or negative about any paper but please be polite. If you are being critical you must mention at least one specific error, otherwise your comment will be deleted as unhelpful.

comments powered by Disqus