Digital Signal Processing


Bivalent Correction of Ieee Std 1800-2017 (Verilog) and Std 1164-1993 (VHDL)

Authors: Colin James III

We evaluate the multivalued logic SystemVerilog in IEEE Std 1800-2017. The classical logic proof tables for the connectives And, Or, Xor, and negations are based on the bivalency of 1, 0, X, Z as 0=~1 and Z=~X. This refutes and corrects the standard. We also retrofit and correct IEEE Std 1164-1993 (SynopsysVHDL) for the same.

Comments: 3 Pages. © Copyright 2016-2019 by Colin James III All rights reserved. Updated abstract at . Respond to the author by email at: info@ersatz-systems dot com.

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Submission history

[v1] 2018-12-15 15:44:58

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