This paper presents a modified design of Area-Efficient Low power Carry Select Adder (CSLA) Circuit. In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry select adder processors and systems. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The major speed limitation in any adder is in the production of carries.
Comments: 4 Pages. International Conference on Electrical, Electronics and Instrumentation Engineering Vol. 1 (2016) p. 114 - 117
[v1] 2016-07-25 01:00:22
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