Digital Signal Processing

   

Design of High Speed Power Efficient Wallace Tree Adders

Authors: Sakshi Sharma, Pallavi Thakur

In this paper FIFB, FIEB and FISB Carry Save Adders and Wallace Tree Adders are designed, encoded in Verilog and simulated using Cadence Software. The 180 nm CMOS technology is used for implementation of adders.The simulation results are compared for power consumption, delay, silicon area and dynamic power dissipation. As the length of inputs increase, power dissipated, silicon area and delay increase in both Carry Save Adder and Wallace Tree Adder. Compared to traditional CSA, the proposed Wallace Tree Adder is found to have shorter delay, lesser power dissipation and lesser silicon area and hence more cost efficient and a better option for real-time applications.

Comments: 5 Pages. International Journal of Exploration in Engineering and Technology, Vol.1 No. 5, ISSN: 2394-7918, May 2016, pg. 18-22

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[v1] 2016-05-10 03:37:47

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