# Digital Signal Processing

## 1607 Submissions

[2] **viXra:1607.0469 [pdf]**
*submitted on 2016-07-25 01:00:22*

### Design of Carry Select Adder using Binary to Excess-3 Converter in VHDL

**Authors:** Brijesh Kumar, Mamta Kulkarni

**Comments:** 4 Pages. International Conference on Electrical, Electronics and Instrumentation Engineering Vol. 1 (2016) p. 114 - 117

This paper presents a modified design of Area-Efficient Low power Carry Select Adder (CSLA) Circuit. In digital adders, the speed of addition is limited by the time required to transmit a carry through the adder. Carry select adder processors and systems. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has been summed and a carry propagated into the next position. The major speed limitation in any adder is in the production of carries.

**Category:** Digital Signal Processing

[1] **viXra:1607.0107 [pdf]**
*submitted on 2016-07-08 17:30:42*

### Analog Computer Understanding of Hamiltonian Paths, and a Possible Digitization

**Authors:** Bryce Kim

**Comments:** 17 Pages.

This paper explores finding existence of undirected hamiltonian paths in a graph using lumped/ideal circuits, specifically low-pass filters. While other alternatives are possible, a first-order RC low-pass filter is chosen to describe the process. The paper proposes a way of obtaining time complexity for counting the number of hamiltonian paths in a graph, and then shows that the time complexity of the circuits is around $O(n \log n)$ where $n$ is the number of vertices in a graph. Because analog computation is often undesirable due to several aspects, a possible digitization scheme is proposed in this paper.

**Category:** Digital Signal Processing