Digital Signal Processing

1605 Submissions

[3] viXra:1605.0212 [pdf] submitted on 2016-05-20 23:27:18

Electromagnetic Force Modification in Fault Current Limiters under Short-Circuit Condition Using Distributed Winding Configuration

Authors: Asef Ghabeli, Mohammad Reza Besmiy
Comments: 17 Pages.

The electromagnetic forces caused by short-circuits consisting of radial and axial forces impose mechanical damages and failures to the windings. The engineers have tried to decrease these forces using dierent techniques and innovations. Utilization of various kinds of winding arrangements is one of these methods, which enable the transformers and fault current limiters to tolerate higher forces without a substantial increase in construction and fabrication costs. In this paper, a distributed winding arrangement is investigated in terms of axial and radial forces during short-circuit condition in a three-phase FCL. To calculate the force magnitudes of AC and DC supplied windings, a model based on the nite element method in time stepping procedure is employed. The three-phase AC and DC supplied windings are split into multiple sections for more accuracy in calculating the forces. The simulation results are compared with a conventional winding arrangement in terms of leakage ux and radial and axial force magnitudes. The comparisons show that the distributed winding arrangement mitigates radial and especially axial force magnitudes signicantly.
Category: Digital Signal Processing

[2] viXra:1605.0088 [pdf] submitted on 2016-05-10 03:37:47

Design of High Speed Power Efficient Wallace Tree Adders

Authors: Sakshi Sharma, Pallavi Thakur
Comments: 5 Pages. International Journal of Exploration in Engineering and Technology, Vol.1 No. 5, ISSN: 2394-7918, May 2016, pg. 18-22

In this paper FIFB, FIEB and FISB Carry Save Adders and Wallace Tree Adders are designed, encoded in Verilog and simulated using Cadence Software. The 180 nm CMOS technology is used for implementation of adders.The simulation results are compared for power consumption, delay, silicon area and dynamic power dissipation. As the length of inputs increase, power dissipated, silicon area and delay increase in both Carry Save Adder and Wallace Tree Adder. Compared to traditional CSA, the proposed Wallace Tree Adder is found to have shorter delay, lesser power dissipation and lesser silicon area and hence more cost efficient and a better option for real-time applications.
Category: Digital Signal Processing

[1] viXra:1605.0012 [pdf] submitted on 2016-05-02 03:36:15

Design of Biometric Fingerprint Image Enhancement Algorithm by using Iterative Fast Fourier Transform

Authors: Shiwani Dod
Comments: 6 Pages. SSRN Electronic Journal

Among all the minutia based fingerprint identification system, the performance depends on the quality of input fingerprint images. In this paper, we have designed and implemented an algorithm of fingerprint image enhancement by using Iterative Fast Fourier Transform (IFFT). We have designed an approach for removing the false minutia generated during the fingerprint processing and a method to reduce the false minutia to increase the efficacy of identification system. We have used fingerprint Verification Competition 2006 (FVC 2006) as a database for implementation of proposed algorithm. Experimental results show that the results of our enhancement algorithm are better than existing algorithm of fast Fourier transform.
Category: Digital Signal Processing