Digital Signal Processing

1604 Submissions

[2] viXra:1604.0287 [pdf] submitted on 2016-04-19 13:09:55

An Efficient Hardware Design and Implementation of Advanced Encryption Standard (Aes) Algorithm

Authors: Kirat Pal Singh, Shiwani Dod
Comments: 5 Pages. Special Issue on International Journal of Recent Advances in Engineering & Technology (IJRAET) V-4, I-2 For National Conference on Recent Innovations in Science, Technology & Management (NCRISTM) ISSN (Online): 2347-2812, Gurgaon Institute of Technology a

We propose an efficient hardware architecture design & implementation of Advanced Encryption Standard (AES). The AES algorithm defined by the National Institute of Standard and Technology (NIST) of United States has been widely accepted. The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. This contribution investigates the AES encryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language (VHDL). Optimized and Synthesizable VHDL code is developed for the implementation of 128- bit data encryption process. AES encryption is designed and implemented in FPGA, which is shown to be more efficient than published approaches. Xilinx ISE 12.3i software is used for simulation. Each program is tested with some of the sample vectors provided by NIST and output results are perfect with minimal delay. The throughput reaches the value of 1609Mbit/sec for encryption process with Device XC6vlx240t of Xilinx Virtex Family.
Category: Digital Signal Processing

[1] viXra:1604.0233 [pdf] submitted on 2016-04-14 15:14:17

Two-Step Authentication that Provides Highly Secure Access to Secure Areas or Resources

Authors: Victor Solovyev
Comments: 6 Pages. 3 figures

A two-step authentication system and method are provided for secure authentication that implements highly secure access to secure areas or resources with disabling the access when the main passcode is compromised. A user, after successfully passing through the passcode of the first-step verification stage, is asked to input an additional secret and presumably easy memorezible code (a pin, second password), or recognize an image for authentication (from a generated set). If during this second-step the user entered information fails to match the correct secret code, then the system sends signal message on intrusion to the user or other designated authorities through a communication device (e.g., email or telephone message) and the access is disabled immediately or after a few permitted attempts. Such authentication, while providing better security and user experience, does not require the usual practice of disabling the access, when the first-step access required information (such as complex alphanumeric password) is entered with errors in repeated access attempts.
Category: Digital Signal Processing