Digital Signal Processing


Performance Imrovement of a Navigataion System Using Partial Reconfiguration

Authors: S.S.Shriramwar, N.K.Choudhari

Dynamic Partial Reconfiguration (DPR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire system interruption. In this thesis, we have implemented a line follower robot for the white line as well as for black line, both these modules are programmed in VHDL. The robot are made to run for white line and it will dynamically reconfigure the FPGA in the run-time for the black line or vice-versa. This design includes two modules one is static and the other is partially reconfigurable regions (PRR) which is a dynamic region. The controllers are the static modules used for controlling the flow of data to and from the reconfigurable modules to the external world (host environment) through busmacros. Whereas white line and black line modules are designed as dynamic modules.

Comments: 8 Pages.

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Submission history

[v1] 2012-08-19 00:36:00

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